1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices and semiconductor memory devices having a data latch function, and more specifically, to improvements of a data latch circuit.
2. Description of the Background Art
A data latch function is mainly constituted by a flipflop circuit, and used in a static memory or a semiconductor integrated circuit device for temporarily holding data. A semiconductor integrated circuit device having such a data latch function together with a setting function or resetting function can achieve easier handling of a signal by controlling an output signal.
The term "reset" herein represents an operation of forcing a latch output to be in an "L" level in accordance with a general idea, while the term "set" represents an operation of forcing a latch output to be in an "H" level. The term "H level" herein represents a power supply potential, and the "L level" a ground potential.
FIG. 7 is a diagram showing a semiconductor integrated circuit device without resetting and setting functions. Referring to FIG. 7, the semiconductor integrated circuit device includes a clock input terminal 4 for receiving a clock signal CLK, a data input terminal 5 for receiving input data DI, and a data output terminal 6 for outputting latched data. The semiconductor integrated circuit device further includes an N channel transistor 10, and inverters 1, 2 and 3. The N channel transistor 10 has its gate electrode connected to the clock input terminal 4, its source electrode connected to the data input terminal 5, and its drain electrode connected to the input of the inverter 1. The inverter 1 has its input terminal connected to the output terminal of the inverter 2 and its output terminal connected to the input terminals of the inverters 2 and 3. More specifically, the inverters 1 and 2 constitute a latch circuit 9. The inverter 3 has its output terminal connected to the data output terminal 6.
FIG. 8 is a timing chart for use in illustration of the semiconductor integrated circuit device shown in FIG. 7. In FIG. 8, a, b, c, and d represent an order of inputting data. Referring to FIG. 8, an operation of the semiconductor integrated circuit device shown in FIG. 7 will be described. The data DI is provided to the data input terminal 5, and the clock signal CLK is applied to the clock input terminal 4. When the clock signal CLK is in the "H" level, the N channel transistor 10 is turned on, transmitting the input data DI to the inverter 1. Thus transmitting data, the N channel transistor 10 is called a transmission gate. The input data DI provided to the inverter 1 is inverted therein, and then applied to the inverters 2 and 3. The inverters 1 and 2 hold the applied data until the next clock signal turns to be the "H" level. Therefore, once the clock signal CLK rises, the data will not be lost if the clock signal CLK falls after that. The inverter 3.inverts the held data and then outputs the inverted data to the data output terminal 6.
FIG. 9 is a circuit diagram showing a semiconductor integrated circuit device having a conventional resetting function. The semiconductor integrated circuit device shown in FIG. 9 is substantially identical to the semiconductor integrated circuit device shown in FIG. 7 with essential differences being that a reset terminal 7 for inputting a reset signal /RESET is additionally provided, and an NAND gate 11 is provided in place of the inverter 1. The NAND gate 11 has two input terminals and one output terminal. One input terminal is connected to the source of the N channel transistor 10 and the output of the inverter 2, the other input terminal is connected to the reset terminal 7, and the output terminal is connected to the input terminals of inverters 2 and 3.
FIG. 10 is a timing chart for use in illustration of the semiconductor integrated circuit device shown in FIG. 9. A description of an operation of the semiconductor integrated circuit device shown in FIG. 9 follows in conjunction with FIG. 10. When the reset signal /RESET is in the "H" level, the output of the NAND gate 11 is decided by the data DI applied from the N channel transistor 10. When the reset signal is in the "H" level, the semiconductor integrated circuit device operates in the same way as the semiconductor integrated circuit device without a latch function shown in FIG. 7.
When the reset signal is in the "L" level, the output of the NAND gate 11 attains the "H" level regardless of data applied from the N channel transistor 10. The inverter 3 receives this "H" level signal and supplies the "L" level output to the output terminal 6. The "H" level output of the NAND gate 11 is applied to the inverter 2, inverted therein, and further applied to the one input terminal of NAND gate 11. Thus, the output of the NAND gate 11 is latched in the "H" level and output data DO is reset to the "L" level. Thereafter, when an "H" level signal is applied to the reset terminal 7, the reset state is released, and the NAND gate 11 and the inverter 2 latch the input data DI (the c-th one in FIG. 1), in response to a rising of the next clock signal. The latched data is applied to the output terminal 6 through the inverter 3.
FIG. 11 is a diagram showing a semiconductor integrated circuit device with a conventional setting function. The semiconductor integrated circuit device shown in FIG. 11 is substantially identical to the semiconductor integrated device shown in FIG. 9 with essential differences being that a set terminal 8 for receiving a set signal set is provided in place of the reset terminal 7, and a 2-input NOR gate 12 is provided in place of the 2-input NAND gate.
FIG. 12 is a timing chart for use in illustration of the semiconductor integrated circuit device shown in FIG. 11. Referring to FIG. 12, an operation of the semiconductor integrated circuit device shown in FIG. 11 will be described.
When an "L" level signal is applied to the set terminal 8, the output of the NOR gate 12 is decided by the input data DI applied to the input terminal 5. This is the same as the operation of the semiconductor integrated circuit device shown in FIG. 9.
When an "H" level signal is applied to the set terminal 8, the NOR gate 12 outputs an "L" level signal regardless of the data at the input terminal 5. The output is applied to the inverters 2 and 3, and the data applied to the inverter 3 (the "L" level) is inverted therein and then applied to the output terminal 6. The data applied to the inverter 2 is inverted therein and then applied to the one input terminal of the NOR gate 12. Thus, the output of the NOR gate 12 is latched in the "L" level and the output terminal 6 is set to the "H" level.
The semiconductor integrated circuit device having a conventional setting or resetting function structured as described above requires a gate circuit having at least two input terminals for additionally providing the setting or resetting function. The conventional device is therefore encountered with the disadvantage that it requires a number of transistors for forming the gate circuit, thus impeding the size of the device from being reduced.